This invention relates in general to a method for fabricating a semiconductor device, and more particularly to a method for forming elevated source and drain regions in an MOS transistor.
The present day semiconductor integrated circuits include many thousands of semiconductor devices interconnected on a single chip of a semiconductor material. As the complexity of the function being integrated into the circuit on the chip increases, more and more devices are crowded onto the chip. Additionally, even as the devices become more complex, the performance of the devices increase as well. In order to accommodate the higher packing density and higher performance, each individual device must be reduced in size and particular attention must be given to reducing parasitic capacitances. At the same time, it is imperative that the process used to fabricate the improved device be both manufacturable and highly reliable.
One device structure which can contribute to reducing both device size and parasitic capacitance is the elevated source/drain structure. In this structure, contact is made to the source and drain regions by a polysilicon electrode which extends from the source or drain regions themselves up onto the adjoining isolation region. The actual source or drain region can be made small and thus low in capacitance. Electrical contacts to the source and drains usually require the dedication of a relatively large area on the chip, but with the elevated source/drain structure, electrical contact is made by contacting that portion of the polysilicon electrode which is positioned on the isolation region so that the active area of the device can be minimized.
Although the elevated source/drain structure is recognized as a structure which will achieve many of the proposed size and performance goals, there has not been a reliable and manufacturable process by which such devices can be fabricated. Consequently, it would be advantageous if a process existed for the fabrication of VLSI devices capable of providing reliable elevated source and drain structures fully integral with other circuit elements and devices.